Now that the limits of microprocessing of devices in LSI production processes are being reached, attention is directed to 3D package technique as one of methods for achieving much tighter integration. In the 3D package technique, LSI chips are longitudinally stacked up thereby increasing the number of devices per unit area. What is important for reducing this 3D package technique down to practice is electrical package technique of how to connect electrical signals between the stacked-up LSI chips. Electrical connections between LSI chips proposed and achieved so far in the art have relied upon a wire bonding process of making connections using metal narrow wires.
Wire bonding has been used in two-dimensional package over the long term, and its application to the 3D package technique would be relatively ready because of years of accumulation of more technical knowledge. To provide electrical connections of signals between the LSI chips by the wire bonding process, however, signals must first be led up to the peripheries of LSI chips, whence they are then connected up to the peripheries of the destination LSI chips using metal narrow wires, and then led down to sites lying in the LSI chips and in need of said signals using wires in the LSI chips. In the wire bonding process, therefore, there is the need for taking hold of wire bonding areas around the LSI chips, leading to a problem that the package area increases with an increase in signal transmission paths between the LSI chips. Further, the number of signal paths between the LSI chips is restricted by the number of bonding terminals located around the LSI chips.
In recent years, attention has been attracted to through silicon via (TSV) technique as another means for making electrical connections between LSI chips (see Non-Patent Publication 1). In the TSV technique, circuits between the LSI chips are directly connected together using TSVs that are longitudinal wires extending through the stacked-up LSI chips, instead of electrically connecting signals by way of wire bonding outside the LSI chips. By wiring LSI chips together using TSVs, the problems mentioned in conjunction with the wire bonding technique are expected to be overcome.
One of important challenges for practical applications of the TSV technique is to embed a conducting material within narrow pores (vias) having a high aspect ratio within a shorter period of time. Although use of copper as a high-conductivity embedding material for the TSV technique is now under study (see Non-Patent Publication 2), yet it takes a 2 hour or longer time to achieve this by copper plating, so there is still the need for shortening that time significantly. As the embedding material, poly-silicon, tungsten, silver or the like in addition to copper are now under investigation (see Patent Publication 1 and Non-Patent Publication 3). Comparisons of these embedding materials are tabulated in Table 1.
TABLE 1Poly-siliconWCuAgConductivity4.0 × 1041.89 × 1055.96 × 1056.3 × 105(Ω−1 cm−1)WiringCVDCVDPlatingVacuumPreparationPrintingPretreatmentSiNWNSi/SiNUnneces-(Formation of(CVD)Ti/TiNsarythe barrier film)Ta/TaN(SputteringOr CVD)PretreatmentUnneces-WCuUnneces-(Formation ofsary(CVD)(CVD)sarythe seed layer)Remarks1*2*3*1*: W is a strategic substance arising concern about stable availability.2*: There is a problem with yields, and pores are likely to occur.3*: Some post-thermal treatments are needed, and there is migration occurring.
Besides, conducting polymers are also being studied as the embedding material. Conducting polymers are resourceful materials that are less costly because of the capability of being used in normal temperature/pressure processes such as coating. However, they have a demerit of having a low conductivity.
By the way, there is a report about a method for co-precipitation of silver and polypyrrole that is a sort of conducting polymer through the following reaction mechanism with a view to applying them to catalyst carriers, marker particles for immunodiagnosis, etc. (Non-Patent Publications 4 and 5).

According to this method, there is a possibility that a material higher in conductivity than the conducting polymers may be filled in vias in simple operations.
However, the material obtained by this method, too, cannot achieve the conductivity high enough to satisfy the requirement for a filler for TSVs, and there is still a problem with production cost, because relatively base metals such as copper cannot be used.
Patent Publications 2 and 3 disclose another process for producing conducting polymer/metal composites, but they fail to give any suggestion of precipitation of composites with the aid of light irradiation or the like.